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TEAM PROJECT · LOGIC DESIGN LAB, NDU

TTL LogicGate Clock

The same clock built twice: first from discrete 7400-series TTL gates and counters with no microcontroller and no firmware anywhere, then again as synthesizable Verilog. 12-hour (with AM/PM) or 24-hour display, a comparator-driven alarm, and every control set by hand.

THE GOAL

Final project for NDU's Logic Design Lab: build a fully working digital clock and alarm using nothing but discrete logic (counters, comparators, and gates), with no microcontroller and no firmware anywhere in the design. Built as a four-person team. The design later got written a second time in Verilog, so the same clock exists both as chips on a breadboard and as RTL you can simulate or put on an FPGA.

  • Separate counter chains for hours, minutes, and seconds, driven by a 555 timer's one-second pulse
  • Switches between 12-hour (with AM/PM) and 24-hour display
  • A 7485 comparator continuously checks the current time against a user-set alarm time
  • Time and alarm are both set entirely by hand, no software interface
  • 4026 decade counters drive the 7-segment displays directly, no display driver code
  • The whole design written again as synthesizable Verilog: five modules, a testbench each
Finished TTL logic gate clock breadboard build showing hours, minutes, and seconds on 7-segment displays

FINAL BUILD

The finished clock across three breadboards: hours on the left, minutes and seconds in the middle, and the alarm set/indicator section on the right with its status LED and button.

HOW IT WORKS

A 555 timer astable oscillator generates the base one-second pulse that drives everything downstream. That pulse ripples through 4026 decade counters chained for seconds, minutes, and hours, each one driving its own 7-segment display directly. A 74157 multiplexer switches the display and counter inputs between normal run mode and set mode, so the hand-operated switches can load a new time or alarm value without disturbing the running clock. A 7485 4-bit comparator sits on the hour and minute counters and the alarm registers in parallel, watching for a match; when it finds one, it trips the alarm output. AND/OR gates (7408, 7432, 74HC21, 74HC86) handle the 12/24-hour mode logic and the AM/PM rollover, while 7474 D flip-flops latch which mode the clock is currently in.

Full circuit schematic of the TTL logic gate clock, showing all counter, comparator, and gate connections

FULL CIRCUIT MAP

The complete connection diagram: every counter, comparator, and gate in the design, from the 555 timer's pulse generator on the bottom right to the alarm LEDs at the top.

THE SAME CLOCK IN VERILOG

The breadboard version can only ever be the one clock sitting on the bench, so the design was written a second time as synthesizable RTL. A parameterized BCD counter module stands in for the 4026 chain, its carry out feeding the next stage exactly the way the ripple counters did. A timekeeper module chains six of those into seconds, minutes, and hours and handles the set-by-hand inputs. A format converter does the 12/24-hour conversion and drives the AM/PM flag, a 7-segment decoder turns each BCD digit into segment patterns, and the top module wires the six display digits plus the AM/PM indicator to a six-bit switch bus for setting hours, minutes, seconds, mode, AM/PM, and reset.

  • Five RTL modules, each with its own testbench, simulated under Icarus Verilog
  • The top-level bench decodes segment patterns back into characters, so it checks the display path end to end
  • Runs across midnight and noon in both display modes to catch the rollover cases
  • Waveforms committed as VCD files alongside the sources
RTL5 VERILOG MODULES
VERIFICATIONTESTBENCH PER MODULE
SIMULATORICARUS VERILOG → VCD

SOURCE ↗

CLOCK SOURCE555 TIMER
COUNTERS4026 DECADE + 7-SEGMENT DRIVE
ALARM7485 4-BIT COMPARATOR
DISPLAY MUX74157 QUAD 2-TO-1
LOGIC7408 · 7432 · 74HC21 · 74HC86
MODE LATCH7474 D FLIP-FLOP
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